Post Doc Evaluation of dynamic partial reconfiguration capabilities through a use case based on CNN F/H

ref : 0021636 | 21 mai 2019

date limite de candidature : 31 déc. 2019

40 48 Avenue de la Republique 92320 CHATILLON - France

votre rôle

Your role is to conduct work on : « FPGA: Evaluation of dynamic partial reconfiguration capabilities through a use case application »

  • Context and state of art

Field Programmable Gate Arrays (FPGA) are increasingly becoming widespread within the industry for a wide category of applications specifically in communications, image processing, data mining and control, due to their ability to meet real-time requirements and due to their highly parallel architecture. FPGAs provide a platform that can be optimally configured based on different performance requirements. The emergence of the partial reconfiguration capability [2] [11], also dynamic, where only parts of the hardware are modified at runtime, without alteration of remaining parts brings advantages to FPGA designs. Logic can be modified in certain areas through reconfiguration while the device remains operational. DPR is attractive when resource requirements of applications are greater than the FPGA's available resources or to multiplex multiple independent acceleration functions (as in the case of Cloud environments). There has been an explosion of research work in DPR in the recent years;

  • Exploit the PR capability to design methodologies to evolve hardware applications: Software Defined Radio, supervised algorithms for classification, CNN based applications such as video, audio or voice processing [2][3][4][9][10].
  • Design methodologies [7][8].
  • Techniques for partitioning, scheduling and optimized mapping of functional blocks on FPGA regions[12]

Furthermore vendors such as Intel and Xilinx provide design toolkits and development suites and this has started to render FPGA computing accessible to a wide audience. OPAE [1] is a community effort to software interface to discover, access, and manage reconfigurable resources, to simplify integration of FPGA acceleration functions into software applications. Platform drivers and libraries handle management and reconfiguration features and provide a simple infrastructure for software developers. In this context, it becomes interesting to study if these frameworks permit exploiting completely the advantages of dynamic partial reconfiguration and to evaluate limitations, for example, constraints on location and shape of PR regions, the number of PR partitions etc. Thus the post-doctoral work will consist of state of art analysis and experimentation through a proof-of-concept use case to evaluate the advantages of partial reconfiguration.

votre profil

The ideal candidate will have a PhD degree in computer science, following an engineering degree in computer science or a relevant field of engineering.

Skills :

  • Embedded systems, FPGA, parallel computation, formal methods for software design,
  • Programming skills (C, C++, Python)
  • Prior experience in deep learning or in computer vision is a plus
  • Autonomy but with motivation for collaborative work within a team

You have a previous job experience in development with FPGA.

le plus de l'offre

The main objective of this post-doctoral work is to :

oExplore parameters and design variables of the target application functions implemented as HW tasks and understand their impact on performance, with the aim to elicit designs that meet target performance metrics (eg. throughput, latency, energy consumption), taking into account the parameters and topology of the target use case,

oProvide in-depth insights on partial reconfiguration, their advantages and design constraints, with the aim to elicit efficient design patterns for Orange workloads, specifically real-time and latency aware workloads.

This objective is expected to be attained through experimentation and proof-of-concept implementation, with a toolkit and development suite to be decided at the beginning of the planned work.

Method and planning

The work will be conducted in the following phases:

oState of art tools and experimentation:

  • Literature covering dynamic partial reconfiguration, design methodologies (if pertinent for the specific target use case)
  • Learning toolkits for programming and managing FPGA-based acceleration functions

oEvaluate the potential of dynamic partial reconfiguration and analysis of factors that affect usability (e.g. overheads, constraints, energy consumption etc ) to understand the benefits that specific features of PR brings, and to identify applications and use cases that can best leverage this PR capability.

oImplementation of a proof-of-concept use case

Convolutional Neural Network (CNN) based applications for computer vision is so far targeted as the use case for prototyping. The highly structured architecture is conducive to mapping to FPGA. Moreover trained networks are available for experimentation, and data is not an issue for testing (inference). Nevertheless the choice of the use case will be confirmed based on maturity and availability of other use cases such as Spiking Networks [5] or Recurrent Neural Networks for network anomaly detection or optimization of radio access networks.


Au sein du département SAP, l'équipe ASO (Automatisation de Services et Orchestration) contribue à l'innovation du Groupe sur les technologies, logiciels et services du domaine de l'infrastructure de virtualisation et automation. Les principales activités au sein de l'équipe sont la gestion de l'infrastructure virtualisée et automation de déploiement, la gestion de la performance et les études des services innovants et virtualisation des services innovants.

Qu'est ce qui fait la valeur ajoutée de cette offre ?

Le post-doc s'effectuera dans un grand groupe international dans le domaine des télécommunications. Vous serez directement impliqué-e dans les problématiques d'infrastructures cloud et de virtualisation réseau du groupe Orange, spécifiquement dans les techniques d'accélération de performances des applications sensibles à la latence. Vous aurez l'occasion de participer à des conférences internationales pour présenter les résultats. Par ailleurs vous auriez la possibilité de collaborer avec les équipes de recherche de l'INRIA dans le cadre de laboratoire commun INRIA / Orange.

Références :

[1] https://01.org/OPAE

[2] An OpenCL Deep Learning Accelerator on Arria 10

[3] Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions, ACM Computing Surveys (CSUR), Stylianos I. Venieris, Alexandros Kouris, Christos-Savvas Bouganis, Volume 51 Issue 3, July 2018

[4] https://software.intel.com/en-us/openvino-toolkit

[5]A methodology for evolving spiking neural-network topologies on line using partial dynamic reconfiguration

[6] Dynamic Partial Reconfiguration implementation of the SVM/KNN multi-classifier on FPGA for Bioinformatics application, Hanaa M. Hussain, Khaled Benkrid, and Huseyin Seker, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

[7] Latency-Driven Design for FPGA-based Convolutional Neural Networks, Stylianos I. Venieris ; Christos-Savvas Bouganis, 2017 27th International Conference on Field Programmable Logic and Applications (FPL)

[8] Mapping Parameterized Dataflow Graphs onto FPGA Platforms, Hsiang-HuangWu et al, Academic Press Library in Signal Processing, Volume 4, 2014, Pages 643-673

[9] Comparison of FPGA implementation of LDPC encoder algorithms, Steffy Johnson ; Nidhi Gaur, 2016 6th International Conference - Cloud System and Big Data Engineering (Confluence)

[10] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ldpc.pdf

[11] FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications, Kizheppatt Vipin, Suhaib A. Fahmy, ACM Computing Surveys (CSUR), Volume 51 Issue 4, September 2018, Article No. 72

[12] Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems, Yi Lu, Thomas Marconi, Koen Bertels, and Georgi Gaydadjiev, J. Becker et al. (Eds.): ARC 2009, LNCS 5453, pp. 216-230, 2009


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